wafer.space Community - My custom ASIC KianV SV32 SoC is now

6:08 p.m.

Super cool! Newbie question: why is the sdram exposed via pins? to allow loading the memory/program externally directly instead of over something like uart? also what are the 20 some "blocks" in the image?

Great questions — SDRAM is external because this process node doesn’t offer large embedded DRAM, only small SRAM blocks.To run Linux you need external memory.

oooh right, makes sense!

What kinda SDRAM can run at 5V?

It runs at 3.3V with 20MHz

How much RAM is required to boot mainline Linux? Like, at minimum?

6:55 p.m.

I’ve done it with as little as 16MiB, booting to busybox with 12MiB free. So could maybe do 8MiB.

1Mx16 Dynamic RAM with 5V power supply: https://www.issi.com/ww/pdf/41C16100.pdf 4 of these and you get your 8MiB for busybox on mainline Linux at a much higher clockspeed

7:21 p.m.

I highly doubt 20MHz at 3.3V is realistic without wait states. My own testing put the switching speed of the GPIOs at 12.5MHz at 3.3V.

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I mean, I did build the Tiny Tapeout Micro Linux SoC. With that thing I could boot Linux with just 8 MB. The SoC should support IPv6 and IPv4 and be comfortable to use — not just boot BusyBox and call it a day. I want to do more with it: MicroPython, C++, NFS, all kinds of stuff.

BusyBox + Lua is a decent setup for me on embedded

8:31 p.m.

(I strongly dislike python)

K

But yeah, this project might be more interesting once we have a native 3.3V SCL and 3.3V IO pad structures.

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